1. Field of Invention
The present invention relates to a single or a plurality of digital systems operating synchronously with a single or a plurality of clock signals, a method for adjusting in timing the clock signals of such a digital system, and a recording medium having a processing program recorded on it, the processing program being executed in the adjusting method.
Particularly, the present invention is very effective in case that the number of digital circuit elements being components of a digital system or in case that the frequency of a clock signal is high.
2. Description of Related Art
A digital system is ordinarily composed of logic elements of three kinds which are an AND element, an OR element and a NOT element, and a memory element called a flip-flop to memorize either of the two states (1 bit) of true (logic value xe2x80x9c1xe2x80x9d) and false (logic value xe2x80x9c0xe2x80x9d).
The most basic flip-flop is composed of three terminals of one input terminal, one output terminal and a clock terminal, and has a function which copies a digital signal of the input terminal to the output terminal at rising of a digital signal called a clock signal applied to the clock terminal and holds this digital signal until rising of the next clock signal.
Generally, a digital system operating according to a finite number of clock signals is called a synchronous circuit, in which the time difference between clock signals reaching the clock terminals of the respective flip-flops has an influence upon operation of the whole system. Generally, a signal line to supply a clock signal to each flip-flop often has a buffer inserted in the course of it or adopts a special circuit contrived in physical wiring, which is called a clock circuit here.
For example, while a time difference of 1 ns is a difference of 1% in case of a clock frequency of 10 MHz, namely, in case of a clock cycle of 100 ns, the same time difference of 1 ns is a difference of 10% in case of a clock frequency of 100 MHz, namely, in case of a clock cycle of 10 ns and needs to be compensated. In short, the higher a clock frequency is, the more accurate a timing adjusting technique needs to be.
A conventional countermeasure to counter a clock timing error in a digital system includes such two ways as;
(1) a countermeasure technique in which a designer performs a manual adjustment so as to make a clock timing error as small as possible at the time of designing a digital system, and
(2) a countermeasure technique of providing an adjusting circuit compensating for a clock timing error in a clock circuit in a digital system.
However, countermeasure (1) cannot solve the following problems. That is to say, electronic circuit elements such as a transistor, a resistor and a capacitor vary respectively in characteristic, and variation of the respective elements is not apparent until a system is actually formed. This is a characteristic particularly remarkably appearing in elements in an integrated circuit. It is a clock timing that is most influenced by this variation, which determines the upper limit of the operating frequency of a digital synchronous system.
In such a way, since variation in these elements cannot be completely grasped at the time of design of a digital system, a technique has been taken which designs and manufactures it allowing a certain range of variation or which measures an actual degree of variation by repeating its trial manufacture. However, this technique has apparently a limit and has not been able to utilize the characteristic of each element to its limit.
As another problem, a manual adjustment has a limit in scale of a hand-leable circuit, and has not been able to adjust the whole of a large-scale digital system such as a computer system as a practical problem. And a technique of separating a large-scale problem into partial problems, the technique being a familiar method in handling a large-scale problem is not preferable due to limiting a range of adjustment.
A problem in countermeasure (2) is that although an adjusting circuit is inserted, with the increase of a circuit scale the adjusting and search space becomes more extensive and results in making it impossible to perform adjustment within a practical time. On the other hand, an adjusting circuit which can perform adjustment within a practical time can adjust only a small part of a digital system and its effect is extremely limited.
In case that the above-mentioned digital system is made as an integrated circuit, it is further characterized by the following two points.
The first point is that the interior of an integrated circuit cannot be modified and must be all determined at design. Thereupon, a technique of inserting an adjusting circuit is taken, but since the adjusting and search space becomes very extensive, it is impossible to perform adjustment in consideration of operation of the whole circuit. If a new technique of the present invention as described later is not used, it is impossible to perform a timing adjustment in consideration of operation of the whole circuit after the integrated circuit chip has been manufactured.
The second point is that elements in an integrated circuit chip are large in variation and variation in parameters (the values of a resistor, a capacitor, etc. and characteristics of a transistor) of the internal elements becomes apparent only after the integrated circuit chip has been manufactured. Therefore, the variation in them has a large influence upon a clock timing, and such a new technique as the present invention described later is indispensable in case of requiring accurate element parameter values in order to utilize characteristics of the elements to their limits.
In a case that a digital system is an ordinary hardware design data library or a hardware design data library which is considered as an object of intellectual property rights, called IP, and is intended to be used by a third party, its functions and interface requirements are publicly disclosed, but more detailed information than an equivalent circuit related to its internal structure may not be publicly disclosed.
In a case of using such IP in an integrated circuit having a high clock frequency, an accurate timing adjustment reaching the interior being treated as an object of the IP is indispensable. However, since the interior is often a black box due to IP rights as described above, in order to manufacture an integrated circuit operating at a high clock frequency while keeping such rights, it is necessary to provide a clock circuit to generate data of the optimum input and output timing for each IP at an external circuit side.
However, since even if the same IP is used, the optimum input/output timing varies in each chip, the prior technique has been unable to manufacture such an integrated circuit.
Additionally, most of the present digital systems use a CMOS technology and in case that a digital system is formed using a CMOS technology, most of a power source current flows when each digital signal changes (from logic value xe2x80x9c0xe2x80x9d to logic value xe2x80x9c1xe2x80x9d or from logic value xe2x80x9c1xe2x80x9d to logic value xe2x80x9c0xe2x80x9d).
If a number of digital signals change at the same time, therefore, a large power source current flows instantaneously and insufficiency of the power capacity makes a power source voltage change and, in its turn, may cause an erroneous operation.
Furthermore, in comparison with a case where a small current flows continuously, when a large current flows instantaneously, the power consumption is made larger and a larger-capacity power source and power feeding lines need to be prepared and these result in making a digital system larger in size.
To decrease an influence of the simultaneous change of digital signals can be attained by finely adjusting the respective signals in timing, namely, the respective flip-flops in timing within a range where the whole system operates correctly, but a conventional technique has been unable to perform such an accurate timing adjustment in consideration of operation of the whole system.
Additionally, an unwanted electromagnetic emission (EMI) generated from a digital system, which has such an influence as making another digital system around it erroneously operate, should be suppressed. This problem is particularly serious in case that a digital system is packaged as a circuit board, and is regulated by various laws of various countries. The EMI is generated when a digital signal changes (from logic value xe2x80x9c0xe2x80x9d to logic value xe2x80x9c1xe2x80x9d or from logic value xe2x80x9c1xe2x80x9d to logic value xe2x80x9c0xe2x80x9d), and an EMI having a large peak power is generated when a number of digital signals change all at once.
As one way for suppressing this, there is a method of reducing the number of digital signals changing at the same time, namely, the number of flip-flops changing at the same time, but it has been impossible to accurately adjust in timing the flip-flops of the whole digital system within a range where the whole digital system correctly operates at a specified clock frequency by means of a conventional technique.
For such reasons a new method for automatically performing a clock signal timing adjustment for each digital system is needed particularly in a large-scale and high-speed system, and the present invention has been made in order to advantageously solving such problems.
In order to attain the above-mentioned objects, a digital system of the present invention according to claim 1 is a digital system performing a specified function by performing a digital process according to a single clock signal or a plurality of clock signals, being provided with;
a plurality of delay elements which are inserted respectively in a plurality of clock circuits supplying the clock signals in the digital system and each of which is composed of a circuit element changing its delay time according to a value indicated by a control signal, and
a plurality of holding circuits for holding a plurality of control signals to be given to the plurality of delay elements, wherein;
the plurality of holding circuits have the plurality of control signals obtained by changing the plurality of control signals which these holding circuits hold by means of an external device according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.
Additionally, a method for adjusting a clock signal of a digital system according to claim 12 is a method for adjusting in timing a single clock signal or a plurality of clock signals of a digital system performing a specified function by performing a digital process according to the single clock signal or the plurality of clock signals, the method comprising the steps of;
inserting a plurality of delay elements respectively in a plurality of clock circuits supplying the clock signals in the digital system,
forming the plurality of delay elements respectively out of circuit elements each changing its delay time according to a value indicated by a control signal,
making a plurality of holding circuits provided in the digital system hold a plurality of control signals to be given to the plurality of delay elements, and
changing the values of the plurality of control signals which the plurality of holding circuits hold by means of an external device according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.
In such a digital system and in such a method for adjusting a clock signal of the digital system;
a plurality of control signals which a plurality of holding circuits hold are respectively given to delay elements which are inserted respectively in a plurality of clock circuits supplying a single or a plurality of clock signals in a digital system and each of which is composed of a circuit element changing its delay time according to a value indicated by a control signal, and
each delay element delays properly and supplies a clock signal to a basic circuit according to a value indicated by each of these control signals. Additionally, an external device changes the values of the plurality of control signals which the plurality of holding circuits hold according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing. xe2x80x9cDelayxe2x80x9d in the present invention includes also negative delay, namely, advancing in addition to positive delay, namely, delaying.
According to a digital system of the present invention and a method for adjusting a clock signal of the digital system of the present invention, in case that characteristics (delay characteristic and the like) of circuit elements associated with the specified function cannot be accurately grasped, or in case that some error occurs in characteristic of the circuit elements in a manufacturing process, or in case that non-uniformity in quality or error in design occurs in clock circuits, or even in case that a basic circuit in a digital system is made to be a black box like the above-mentioned IP and its composition is not clear, since it is possible to perform adjustment so that the digital system can correctly operate by absorbing a timing error of a clock signal, it is possible to obtain a higher performance related to the function than a prior art with a less design effort than the prior art, and obtain a larger-scale and higher-speed digital system than a digital system obtained by the prior art, and further prevent deterioration of the performance of the digital system caused by variation of the circuit elements and the like.
Additionally, according to a digital system of the present invention and a method for adjusting a clock signal of the digital system of the present invention, since it is possible to accurately adjust in timing the flip-flops of the whole digital system and slightly shift the flip-flops in operation timing within a range where the whole digital system correctly operates, it is possible also to suppress the increase in size of the digital system due to the increase of power consumption and the occurrence of unwanted electromagnetic emission (EMI), caused by simultaneous change of digital signals.
Hereupon, what degree a digital system correctly operates to can be represented by an evaluation function F having as parameters the delay values of all adjustable delay elements. To operate correctly a digital system is equivalent to finding a solution of the above-mentioned evaluation function F. The inventors of this application have found that a genetic algorithm can be applied to a clock timing adjustment of a digital system, paying their attention to this point.
The genetic algorithm is one of probabilistic search techniques and an algorithm which (1) acts effectively in a wide-area search, (2) does not need derivative information such as differential values other than an evaluation function F, and (3) has an easy implementability. In the present invention, therefore, as described in claims 2 and 13, a genetic algorithm may be used for changing a plurality of control signals by means of the above-mentioned external device.
Additionally, although a clock circuit is often implemented so as to have a tree structure, in addition to a method of arranging adjustable delay elements only at leaf parts of the tip of a tree structure as described above, namely, only at flip-flop parts, a method of arranging them also at branch points in the course of a tree structure is conceivable. In this case, an adjustable delay element arranged at a branch point functions so as to add a delay to adjustable delay elements existing ahead of this point and has a function of making smaller the delay elements being at the tip parts. Therefore, it has the possibility of making smaller the total size necessary for implementing adjustable delay elements.
On the other hand, in recent years, a genetic programming obtained by applying a contrivance making it possible to handle a chromosome of a tree structure to a genetic algorithm has been also known. In the present invention, therefore, in a case that adjustable delay elements are arranged along a tree structure of signal lines of a clock in such a way, a genetic programming may be used for changing a plurality of control signals by means of the external device, as described in claims 3 and 14.
Additionally, in the present invention, as described in claims 4 and 15, a control signal may be changed by the external device as raising the frequency of a clock signal in stages, and by doing so it is possible to operate a digital system at a higher clock frequency, in its turn, at a more high-speed operating state.
Additionally, a digital system of the present invention according to claim 5 is characterized by being provided with a setting device in the digital system itself instead of using an external device in the digital system according to claim 1. A method for adjusting a clock signal of a digital system of the present invention according to claim 16 is characterized by being provided with a setting device in the digital system itself instead of using an external device in a method for adjusting a clock signal of a digital system according to claim 12.
According to such a digital system of the present invention and such a method for adjusting a clock signal of a digital system of the present invention, the same action and effect as the previous digital system and method for adjusting a clock signal of a digital system can be obtained. Furthermore, since a setting means which the digital system itself has is used instead of an external device, further action and effect of making it possible to perform adjustment by a digital system itself at any time and at any place can be obtained.
Also, in a digital system and a clock signal adjusting method of the present invention, as described in claims 6 and 17, a genetic algorithm may be used for changing a plurality of control signals by means of the external device.
Also, in a digital system and a clock signal adjusting method of the present invention, as described in claims 7 and 18, a genetic programming may be used for changing a plurality of control signals by means of the external device.
Furthermore, in a digital system and a clock signal adjusting method of the present invention, as described in claims 8 and 19, a control signal may be changed by the setting means as raising the frequency of a clock signal in stages.
Additionally, a digital system of the present invention and a digital system in a method for adjusting a clock signal of a digital system of the present invention as described above may be formed as an integrated circuit, as described in claims 9 and 20, and by doing so it is possible to optimally adjust a clock signal in an integrated circuit in which variation of circuit elements is not apparent until the integrated circuit is actually manufactured.
Additionally, a digital system of the present invention and a digital system in a method for adjusting a clock signal of a digital system of the present invention as described above may have a pipeline structure, as described in claims 10 and 21, and if doing so, since it is possible to perform adjustment in parts and in stages as utilizing a data dependent relation of a pipeline structure, it is possible to reduce an adjusting and search space and shorten an adjusting time.
Furthermore, a digital system of the present invention and a digital system in a method for adjusting a clock signal of a digital system of the present invention as described above may be formed as a circuit board, as described in claims 11 and 22, and if doing so, it is possible to absorb a slippage in clock timing caused by non-uniformity in constituent elements or constituent materials of a clock circuit in a digital circuit board manufacturing process or errors in design and adjust the digital circuit board so that it performs no erroneous operation.
Additionally, a digital system of the present invention as described above and the external device and the setting means in a method for adjusting a clock signal of a digital system of the present invention may be each composed of a computer such as a personal computer, a microcomputer or the like, as described in claims 23 and 24, and if doing so, it is possible to easily and securely perform in a short time a process of changing the values of a plurality of control signals which a plurality of holding circuits hold according to a probabilistic search technique so that the digital system operates correctly in relation to operation timing.
Furthermore, a recording medium of the present invention according to claim 25 is characterized by having a processing program recorded on it, which processing program is executed by an electronic computer and changes the values of a plurality of control signals which a plurality of holding circuits hold according to a probabilistic search technique so that a digital system operates correctly in relation to operation timing in a method for adjusting a clock signal of a digital system as described in claim 23 or 24.
According to such a recording medium, it is possible to record and store a processing program to be executed by an electronic computer for a digital system of the present invention and for a method for adjusting a clock signal of a digital system of the present invention and adjust a clock signal at an arbitrary place. As such a recording medium, a data recording medium such as a hard disk, a CD-ROM, an optical disk and the like, and a memory element such as a ROM, a RAM and the like can be used in addition to a flexible disk.